Hello World" (or "Olá Mundo" in Portuguese) is a name used in programming language tutorials for the implementation of a simple and functional first program. In the programming world, "Hello World" typically writes the phrase "Hello World!" in a text terminal. In this tutorial, you will learn how to design a digital circuit that writes "OLA!" on the seven-segment display of the Pitanga Community board.
In this tutorial, you will learn how to:
Design a circuit that prints on the seven-segment display
Describe in Verilog a circuit that prints the letter 'L'
Map the ports of a Verilog circuit to the Community board display
Compile and prototype a circuit that prints the letter 'L' on the Community board
Read and understand the summary report of a digital circuit project
Compile, run and interact with the "Ola Mundo" project on the Community board.
Understanding the circuit project
The digital circuit for the implementation of this project is very simple and does not require much knowledge in digital logic. The only work to be done is to connect the switches to the seven-segment display, which will be done through the Pitanga virtual chip. The segments of the Pitanga Community board display are active at logic level '1' (VCC). Therefore, we need to connect the correct segments to logic level '1' (VCC) to write the letter 'L' on the display. Below is the schematic of the circuit project:
Note that the device that connects the sw1 key to the seven-segment display is a buffer (represented by triangles). There are three buffers, one for each segment of the display that forms the letter 'L'. These buffers are present in the Pitanga programmable virtual chip and will be described in Verilog in the following section.
Describing the circuit in Verilog
The Pitanga virtual chip has several logic cells (or logic gates). Among them, we have the buffers, which are gates that only transmit the input signal to the output without making any changes to the signal. Below, we have a slightly more detailed schematic of the same circuit, indicating that the buffers are cells of the Pitanga virtual chip. These cells will be used to connect the sw1 key to the seven-segment display.
From the schematic, let's describe the circuit that interfaces between the seven-segment display and the sw1 key on the Community board. Initially, we will declare the interface signals, which are: L[2], L[1], L[0], and chave_l. These signals must be encoded in the module construction in Verilog, as indicated below:
module ola_mundo(
// Sinal que liga e desliga a letra 'L'
input chave_l,
// Vetor de sinais conectado aos segmentos
// que formam a letra 'L'
output [2:0] L
);The output signal L is a vector. Vectors in Verilog are declared using square brackets. The individual signals of the L vector can be accessed as follows: L[0], L[1], and L[2].
Next, right below the module construction, we will describe the logic of the digital circuit, which in this case are the three buffers connected to the external key chave_l.
// Circuito que liga e desliga os
// segmentos que compoem a letra "L"
buf(L[2],chave_l);
buf(L[1],chave_l);
buf(L[0],chave_l);And finally, we will add the endmodule directive to close our module ola_mundo.
endmoduleThe complete Verilog code for the circuit is shown below:
module ola_mundo(
// Sinal que liga e desliga a letra 'L'
input chave_l,
// Vetor de sinais conectado aos segmentos
// que formam a letra 'L'
output [2:0] L
);
// Circuito que liga e desliga os
// segmentos que compoem a letra "L"
buf(L[2],chave_l);
buf(L[1],chave_l);
buf(L[0],chave_l);
endmoduleMapping the Verilog circuit onto the Community board
The circuit is ready and described in Verilog, but it still needs to be connected to the components of the Community board (switch and display). Each component on the board has a name, which can be identified by the silkscreen, except for the individual segments of the display. To find out the name of each segment of the display, we need to use the figure below:
Now that we know the names of the component identifiers, we will connect the input and output ports of the Verilog circuit to the board components. For this, a text file will be necessary. This file should have the same name as the Verilog module, adding the .pinout extension to the end.
// Porta Verilog Componente da Placa
// Mapeia portas de entrada para as chave sw1
chave_l = sw1;
// Mapeia portas de saida correspondendo a
// letra 'L' para o display de sete segmentos
L[2] = segd2.f_on;
L[1] = segd2.e_on;
L[0] = segd2.d_on;Note that the mapping file represents, in text form, the schematic indicated in the figure below:
With this step completed, we move on to the process of compiling and prototyping the project.
Compiling the project
The compilation process translates the files ola_mundo.v and ola_mundo.pinout into the logic cells available in the Pitanga chip. It is through compilation that the digital circuit is built. To perform the compilation, follow the instructions below:
1) Open the Community board.
. pitanga.sh
python pitanga.pyWindows users can open the Community board by double-clicking on the Pitanga link.
2) Click on the "Upload Files" button and select the ola_mundo.v and ola_mundo.pinout files. Then, click on "Run".
If you have not made any coding errors in Verilog, the report with the project summary will be printed in the text terminal. In this report, you will notice that the designed buffers are accounted for in the last row of the first column.
DESIGN SUMMARY REPORT
module : ola_mundo
design file: ola_mundo.v
pinout file: ola_mundo.pinout
Total number of wires: 0
Total number of cells: 3
Cell Instances Cell Instances Cell Instances
-----------------------------------------------------------------------------
AND2 0 | NAND2 0 | XOR2 0
AND3 0 | NAND3 0 | XOR3 0
AND4 0 | NAND4 0 | XOR4 0
OR2 0 | NOR2 0 | XNOR2 0
OR3 0 | NOR3 0 | XNOR3 0
OR4 0 | NOR4 0 | XNOR4 0
-----------------------------------------------------------------------------
BUF 3 | INV 0 | DFFRSE 0
Cells utilization: 3/500 cells (0.6 %).3) Finally, click on the sw1 switch and check if the letter 'L' appears on the segd2 display. The expected result is shown in the figure below.
If you were able to print the letter 'L', then it will be easy to write "OLA" on the Community board display. Just replicate the concept of this project for the letters 'O' and 'A'. Take some time and try it for yourself. Otherwise, go to the next section.
Prototyping "Ola Mundo" on the Community board
The "Ola Mundo" project has the following behavior on the Community board:
sw2: enables/disables the letter 'O' on the segd3 display.
sw1: enables/disables the letter 'L' on the segd3 display.
sw0: enables/disables the letter 'A' on the segd3 display.
The files for this project are ola_mundo.v and ola_mundo.pinout. These files are located below and must be compiled on the Pitanga chip. If you are unsure how to do this, follow the steps indicated in the previous sections.
ola_mundo.v
ola_mundo.pinout
The result of the compilation will be the video indicated at the beginning of this tutorial. This project has 15 buffers and uses 3% of the available cell capacity on the virtual Pitanga chip. The project summary is shown in the following report:
DESIGN SUMMARY REPORT
module : ola_mundo
design file: ola_mundo.v
pinout file: ola_mundo.pinout
Total number of wires: 0
Total number of cells: 15
Cell Instances Cell Instances Cell Instances
-----------------------------------------------------------------------------
AND2 0 | NAND2 0 | XOR2 0
AND3 0 | NAND3 0 | XOR3 0
AND4 0 | NAND4 0 | XOR4 0
OR2 0 | NOR2 0 | XNOR2 0
OR3 0 | NOR3 0 | XNOR3 0
OR4 0 | NOR4 0 | XNOR4 0
-----------------------------------------------------------------------------
BUF 15 | INV 0 | DFFRSE 0
Cells utilization: 15/500 cells (3.0 %).Conclusion
Congratulations! You have just prototyped a digital circuit without using FPGAs. With the help of the virtual Community board and the programmable Pitanga chip, you gained the experience of developing a digital circuit in Verilog without spending a penny on buying protoboards or FPGA-based boards. This same Verilog can be compiled on a real board, functioning in the same way, as long as the real board has a seven-segment display.
Did you know that the Student board has a faster Pitanga chip with more logic cells than the Community board? And that the Student board has no user limit? Then, consider subscribing to one of our plans. Contact us!
Commentaires